1. Field of the Invention
The present invention relates to a mobile communication system. More particularly, the present invention relates to an apparatus and method for controlling a low-voltage memory in a mobile communication system.
2. Description of the Related Art
In a mobile communication system, all digital chips include a logic part and a memory part therein. Generally, a Static Random Access Memory (SRAM) cell type memory is used as a memory for the digital chip.
Errors which may be generated in the memory can be classified into three types as described below, which can be addressed as follows.
Hard Error: a hard error refers to an error wherein a certain bit cell is permanently damaged due to a defect generated during semiconductor manufacturing processes so that it cannot be written to and/or read from. An error bit location (hereinafter, referred to as an error location) is determined in the manufacturing processes, and cannot be changed after the manufacturing processes have been completed. Therefore, a memory cell repair technique has been widely used to reroute the error location to a prepared spare cell when the error location is identified after the manufacturing processes are completed. All contact to a word line including bits with an identified error is achieved by transferring an address to a prepared spare word line. Transfer of the address is programmed through an eFuse in a facility where the chip is manufactured. Since corresponding word lines can be wholly replaced according to this method even when only one error is generated, a redundancy bit may be wasted. Further, only errors which are previously found in the manufacturing processes can be repaired, while it is impossible to repair errors (soft error, aging, etc.) which are generated after the completion of the manufacturing processes.
Soft Error: α-particles which come from beyond the Earth or are generated on the Earth have a small size and a high energy level. Accordingly, the α-particles can delete values stored in memory cells in a case of colliding against internal physical components of a memory. This is called a soft error. The soft error can be generated any time, and a prediction of soft error generation is impossible. However, the memory can be recycled by writing values on the bit cells again since the bit cell is not physically broken by the soft error. In order to correct the soft error, Error Correction Codes (ECC) (for example parity) are respectively stored to correspond to each data of the memory. Then, the error correction is performed by reading both the corresponding error code and the data at each memory access time to identify whether errors are generated. A general cache controller provides the EEC technique for the soft error. In a soft error correction scheme, many redundancy bits are required to store the EEC for all memory words. Further, since the errors are processed through software by a Central Processing Unit (CPU) when the errors are generated, a performance penalty is increased. In a case that the errors are processed by hardware, hardware complexity is determined depending on how many bit errors in a word line can be processed. Generally, the error correction scheme can support a 1 bit error correction or a 2 bit error detection because it is impossible to perform an error correction for the 2 bit error.
FIG. 1 is a graph showing an error frequency due to a voltage according to the related art.
Low-Voltage Error: In the case of a memory, as shown in FIG. 1, a failure frequency in a writing operation increases as a voltage of an electric power source is lowered. In a digital circuit design of the related art, chips are designed to operate at a high-voltage of the electric power source, in which writing failure is not generated at all. The opportunity to reduce the electric power of the chips is thus greatly restricted by the memory requirements. This failure is defined as an error caused by a low-voltage condition (a low-voltage error). The probability of persistent low-voltage error is in inverse proportion to a log-scale for voltage, and an error rate increases as the voltage is lowered.
The aforementioned memory cell repair technique and soft error ECC technique have problems as described below.
(1) Problems of the memory cell repair technique:
An error location relating to a low-voltage error can be identified when processes are completed. Therefore, it is possible to apply a cell repair technique using eFuse. However, to implement the cell repair technique, an area for the added eFuse and for a redundancy word line used for changing the entire word line is greatly increased. Further, since the number of the corresponding spare word lines linearly increases as the number of errors increases, it is difficult to predict the number of the spare word lines in advance. Accordingly, there is a necessity for preparation of sufficiently large redundancy cells and eFuse, resulting in the increase of cost for securing the area.
(2) Problem of the soft error ECC technique:
A soft error ECC technique of the related art will be described. Basically, since the soft error ECC technique is prepared for a case of failing to identify an error location previously, error codes for all error regions must be stored. Further, the detection of errors is carried out by an added hardware/software logic, but the error correction is transferred to an exception handler so as to be processed by a software. It is determined that a performance penalty due to a software error frequency is lowered when the software error frequency is very low. Accordingly, there are problems as follows when the soft error ECC technique is applied to correct the ‘low-voltage error’.
Firstly, since the ‘low-voltage error’ is permanent under the corresponding voltage of the electric power source, errors are always generated in the case of contact with a corresponding address. Accordingly, it is determined that the error frequency greatly increases (in the case of soft errors, the error frequency can be significantly decreased because the errors disappear when a rewriting operation is performed again). However, there is still a problem in that the performance penalty greatly increases when the errors are corrected by software.
Secondly, it is necessary to carry out an ECC detection process for all writing contact and an ECC generation process for all reading contact. Since an error location of a ‘low-voltage error’ is previously determined, it is necessary to perform a corresponding process for contact with a word line where an error is generated. However, the related art does not classify these processes. Accordingly, there is still a problem in that the performance penalty increases even at a time of contact with an area having no error.
The above information is presented as background information only to assist with an understanding of the present disclosure. No determination has been made, and no assertion is made, as to whether any of the above might be applicable as prior art with regard to the present invention.